As a member of the IEEE Standards Association’s Corporate Advisory Group, I had the pleasure of traveling to India to participate in a seminar, “Global Standards at IEEE”, and in outreach meetings with various organizations and companies. This was my first trip to India, and I must say it was amazing.

During the outreach with the India Semiconductor Association (ISA), I was intrigued by Mr. Anil Gupta’s discussion about challenges facing India in the electronics market and potential solutions to address them. Mr. Gupta is currently a board member of the executive council of the ISA and an eloquent speaker. I was educated by his brief talk – which included a standards element – and I’d like to share a summary with you.

Presently, India’s consumption of electronic products is roughly $40-45B. Its engineering contribution to this market is around 4%. (That’s a fairly small number.) Over the next 10-12 years, India’s electronics consumption could rise to $400B. If the contribution rate continues at its current level – around 4-5% – India’s foreign exchange reserve of $280B would get exhausted just by its electronics consumption, presenting another challenge to the country’s economic condition.

The Indian government recognizes this situation and is thinking about what India can do to better balance the contribution side. The government doesn’t want to create a barrier to entry of foreign products to their own consumers. If Indian consumers are not prohibited from purchasing good products from anywhere, this benefits the Indian consumers. The Indian government thinks (and I agree) that instead of setting up trade barriers, a better way to balance their foreign exchange is to boost local (quality) production. Giving incentives to increase local production could be one of several avenues to make this happen over the next decade. Standards, too, are able to help a lot when it comes to increasing product development. Instead of Indian engineers having to come up with everything on their own, they can leverage standards to contribute right away.

In India today, there are some pockets of local production for the electronics market, and in the EDA space there’s quite a bit of activity, such as PDK development and IP creation with SystemVerilog. There’s also increasing production in embedded software and application software. In academia, there is some research going on, but it’s still limited.

India’s future could include lots of integration – i.e., product components coming to the country for assembly into complete products. Infrastructure is needed, of course, but standards would help integrators take advantage of product integration industries.

India’s future could also include a larger number of PhD candidates. The ISA would like to incentivize an increase in the number of PhDs. Presently, there isn’t much need for PhD’s to do “regular” work – tasks that could be considered menial. There’s not much demand today for PhDs because organizations (companies) are mainly performing implementation as opposed to research and development. And Indian PhD candidates are trained mainly in the theoretical instead of in applied fields which can help improve local product development and production. To effect the end of  PhDs ready to aid in boosting local production, the starting place is with the faculty – improving their knowledge base and their teaching materials (curricula).

The next decade is critical to India. The ISA believes the shift in academia is coming and industry will also move forward.

DVCon 2010 starts this Monday, February 22, at the Doubletree Hotel in San Jose, CA. So far, the numbers are up over last year, and we’re expecting a good crowd.

To date, 483 attendees have registered, while last year at this time there were 475.

In addition, the number of papers submitted was greater than last year, and we added an extra day to accommodate more tutorials.

Don’t let the floor plan fool you – the diagram is deceiving. In 2010, there will be 26 exhibitors, one more than in 2009.

Watch for DVCon-related tweets by searching for the hashtag, #dvcon. Find blogs posts, articles, photos, and videos by Googling dvcon.

See you at DVCon!

The Accellera standards organization has been in existence for 10 years now. I remember like it was yesterday when the boards of directors of Open Verilog International (OVI) and VHDL International (VI)decided that merging the two organizations made sense for the industry. The “standards war” between Verilog and VHDL had ceased to be interesting, and the two hardware description languages were coexisting fairly peacefully. Forming a single organization to oversee the development and adoption of standards for language-based design of integrated circuits made a lot of sense.

The merged organization was named Accellera, and it brought efficiency and focus to standards development in the design automation industry. (Some people thought the name sounded like a car or a vegetable, but I thought it had a nice ring. Gabe Moretti tells the naming story on his blog.)

Several of us had been representatives on both of the OVI and VI boards, so it was a relief to attend half the number of meetings while accomplishing the same amount of – or even more – work towards providing standards for the industry. I recall one day going to a VI board meeting in the morning where people said, “Oh, those Verilog guys…” and then going to an OVI board meeting in the afternoon where people said, “Oh, those VHDL guys…” I kept thinking since “those guys” are “us guys” it sure would be nice to have just one board.

Over the past decade, Accellera has had many successes. Obviously, they have provided numerous market-relevant, well-adopted standards for improving the chip design process. Two of my favorites are SystemVerilog and the Unified Power Format (UPF), both of which are now IEEE standard 1800 and 1801, respectively.

SystemVerilog’s widespread adoption is witness to its success.Starting out with technical donations from Accellera member companies BlueSpec, Mentor Graphics, Motorola, Novas, Real Intent, and Synopsys – with additional contributions from user companies – SystemVerilog expanded upon the long-time industry standard language, Verilog, to address modern design challenges.

Speaking of SystemVerilog and the IEEE, another noteworthy accomplishment of Accellera is the key role it played in supporting the IEEE Standards Association as it established its corporate standards program. SystemVerilog was the second standard to go through the entity-based (one company, one vote) standardization process of the IEEE. It helped pave the way for about 20 corporate standards projects that have been completed or are currently underway in the IEEE.

One of these corporate standards is 1801, which began in the IEEE when Accellera transferred its UPF standard to them. UPF was developed in record time – less than 6 months from the official start of the working group – and arguably, at a reasonable cost to the industry. I was part of the Accellera working group that produced UPF. When it was finished, I made some rough calculations to estimate how much the companies had paid for their employees to develop UPF. For the 9 month period from concept to completion, I counted the number of people in the group, estimated how much of their work week they spent on the standard’s creation, and included an approximation of how much time employees of two standards organizations (Accellera and Si2) spent discussing the landscape for UPF. Not scientific, but interesting anyway, my guesstimate was that 7.3 man-years were invested by the UPF working group. Using a fully-burdened hourly rate of $200, the total cost would have been about $3M. Contrast this to the estimate of 100 man-years (see the last paragraph of the article) that were spent developing the Common Power Format (CPF). That would have been a cost of over $41M! These figures may have been greatly under- or overestimated, but to me it shows the value of cooperation among competitors when producing an industry standard.

Accellera is going to celebrate its 10th birthday with a lunchtime event at DVCon on Tuesday, February 23. I hope you join me in wishing Accellera many more decades of success.

One of my favorite conferences is EDP – Electronic Design Processes. The 17th EDP symposium will be held on April 8-9 2010. As always, the venue is the Monterey Beach Hotel in beautiful Monterey CA. What I like about EDP is its intimacy and sharing of ideas about how chip design can be done better and where technology might be headed. Participants are industry veterans, company leaders, respected academics, and regular people like me who just soak it in. During the presentations, conversations start up and debates can result. Unlike presentations at large conferences which can be mostly one-way communication, EDP’s talks engage the audience.

There’s still room in the program for some good talks, so if you’d like to present an interesting topic, the organizers want to hear from you. They welcome presentations on a wide range of subjects – but no product commercials, please. The submission deadline is February 26.

This year there will be an emphasis on multi-processing (especially for, but not limited to, EDA) and on 3D ICs. There will be a power(ful) panel too, but at this point, EDP organizers see multi-processing as “hotter” than power. Other topics may include cloud computing, DFM, and the analog revolution (is there one?).

A special part of EDP is the beach walks. There’s nothing like a refreshing walk with stimulating conversations among friends. It was during one of these walks that a colleague convinced me that global warming is real.

EDP is sponsored by the IEEE’s Computer Society and Design Automation Technical Committee. Early registration ends March 1, so if you like valuable workshops and like to save money, sign up this month.