For the disbelievers among you, I really, really was not at DAC this year! If you think you saw me, it was no doubt my evil twin sister attempting to fool you.  Nevertheless, standardization in EDA continued nicely for the Open SystemC Initiative (OSCI).

At DAC in Anaheim, OSCI announced the completion of the SystemC TLM-2.0 standard. The new TLM-2.0 interface standard enables SystemC model interoperability and reuse at the transaction level. This is essential to help further adoption of ESL methodologies, and especially virtual platforms, for pre-silicon embedded software design. You can find more information and views in the blog of my colleague, Frank Schirrmeister.

While the birth of SystemC in 1999 had its share of labor pains (no standard begins in a completely friendly environment), I think it’s safe to say that today it is a “peaceful standard”. There is little controversy at present, and Synopsys, along with our two biggest competitors, jointly pushed TLM-2.0 through the working group together with other EDA and customer partners. Our support at Synopsys, shown in our related press release, is proof that SystemC is alive and well within Synopsys to enable our system-level tools for customers involved with pre-silicon embedded software development and embedded software verification.

We at Synopsys have already fully endorsed TLM-2.0.  We view TLM-2.0 as an important step to help further SystemC’s adoption as the virtual platform infrastructure for embedded software development.  Our system-level solutions team has been very active in helping drive standardization after we contributed key virtual platform technology to OSCI in January 2007.  Going forward, we will support SystemC TLM-2.0 in our Innovator and DesignWare® System-Level Library products.

What is impressive about the TLM-2.0 standardization is the number of supporters it has throughout the industry.  OSCI gave out a quote sheet along with their press release which I’m sure they’d be happy to distribute upon request.  The completion of TLM-2.0 was applauded and endorsed by almost 30 companies and organizations representing users, IP providers, EDA suppliers, and service providers. The industry is essentially pledging interoperability.

It’s good to see the cooperative side of the standards game.

EDA standards blog The Standards Game
SystemC OSCI Open SystemC Initiative
Transaction-level modeling TLM TLM-2.0

There are dozens of standards-setting and standards-development organizations in the design automation industry.  My company is a member of more than 35 of them (yes, it’s a hefty bill)!  Of all of them, the most venerable is the IEEE Standards Association (IEEE-SA).  Since I’ve spent the past couple of days with them, I thought I’d give you some interesting information about the IEEE and the IEEE-SA. (For my non-engineering readers, the IEEE is the Institute of Electrical and Electronics Engineers.  In other words, it’s our industry’s professional association, like the AMA is for medical doctors. So you can be cool in front of others, the “IEEE” is pronounced “Eye-triple-E” instead of “Eye-E-E-E”.)

The IEEE is a global, non-profit organization for scientific and educational advancement. Its vision is “to advance global prosperity worldwide by fostering technological innovation, enabling members’ careers, and promoting community”. It’s the world’s largest technical professional society, consisting of more than 376,000 members who live and work in over 160 countries!

Here are some statistics about IEEE members:

- 50% work for industry, 21% in academia, 10.3 % in government (OK, you mathematicians, the rest are retired or students)

- 67% have a postgraduate degree

- 29% have PhDs

- 91% are male, 9% are female (now *here’s* a topic for discussion at a later time)

- 65% are from the Americas, which is a decrease of 5% from 2003

- 17% are from Europe, the Middle East, and Africa, which is an increase of 3% from 2003

- 18% are from Asia (the fastest-growing region), which is an increase of 2% from 2003

The IEEE fosters technical innovation in many areas through its 38 societies and 6 technical councils which represent a wide range of technical interests. The IEEE holds more than 500 international conferences annually (how many have you attended?).  Plus, it publishes over 30% of the world’s literature in its fields with more than 1.7 million documents in the IEEE/IET Electronic Library! 

The IEEE-SA is the organization within the IEEE that develops and promotes its worldwide standards. The standards activities are sponsored by the relevant societies and councils.  For instance, all EDA standards have sponsorship from the Computer Society. The IEEE-SA Board of Governors (responsible for policy) oversees both the Standards Board (responsible for the standards process) and the Corporate Advisory Group (responsible for the entity-based standards process).

Today, the IEEE offers more than 900 active industry standards and has 400 standards projects in progress.  The work is performed by 15,000 volunteers (I’m one of them, of course).  There are 7,000 individual members and more than 80 corporate members of the IEEE-SA. Standards are offered and developed in a variety of areas including:

Aerospace Electronics
Bioinformatics
Broadband Over Power Line
Broadcast Technology
Electromagnetic Compatibility & Safety
Electronic Design Automation
Information Technology
Medical Device Communications
Nanotechnology
National Electrical Safety Code
Organic Components
Portable Battery Technology
Power Electronics
Power & Energy
Radiation/Nuclear
Reliability
Transportation Technology

The IEEE’s standards portfolio ranges from long-established engineering practices to leading-edge technologies. Its intellectual property policy is regularly updated to reflect modern understanding of IP in a standards-development arena.  (Keep watching the Rambus case - I wonder if it will end up in the Supreme Court.) Its standards reflect the standardization principles as stated by the World Trade Organization.

I would venture to say that the reason IEEE standards have so much cachet, integrity, and widespread acceptance is because they are developed under five principles: 

Due process
Openness
Consensus
Balance
Right of appeal

I also want to mention the IEEE-SA’s collaboration with other international standards organizations. The IEC (International Electrotechnical Commission) has 30% of its existing standards offering built upon IEEE standards.  There is a partnership agreement in place between ISO (International Organization for Standardization, according to their website - don’t ask me why it’s not IOS) for joint development and rapid adoption.  The IEEE is a member of all 3 sectors of the ITU (International Telecommunication Union) which are Telecommunications, Radiocommunications, and Development.

The IEEE has been developing standards for more than 100 years. I’d say it’s hard to argue with the IEEE’s experience and easy to trust that the IEEE is a very good place to develop standards.

EDA standards blog The Standards Game
IEEE IEEE-SA IEEE standards

For the first time in 20 years, I’m not going to DAC.  Really.

Instead, I will be in New Jersey, participating in IEEE Standards Association meetings which just happened to coincide with this year’s DAC.

Here are a few of the things I will miss at DAC:

Hanging out with my fellow bloggers in the Synopsys booth as they meet and greet their readers.

Working in the Synopsys standards booth #1541 which features VMM, IPL, and UPF.

Sunday

WORKSHOP: Design and Verification of Low Power SoCs: An Application Oriented Approach <details>

Monday

WORKSHOP: Women in Design Automation: Networking, Negotiation, and Nonsense: Achieving Career Balance in an Unbalanced World <details>

WORKSHOP: Introduction to Chips and EDA for a Non-technical Audience (to be taught by the dynamic Pamela McDaniel in my place) <details>

LUNCH: Interoperable PDK Libraries: “The proof is in the pudding!”<details>

PAVILION PANEL: Student design contest <details>

RECEPTION: Synopsys/Sun university event <details>

Tuesday

BREAKFAST: AMS Verification and Moore’s Law… solutions for 45nm and beyond. <details>

WORKSHOP: Effective Technical Writing <details>

LUNCH: VMM User Forum: Methodology Beyond Base Classes <details>

FORUM: Accellera Technical Committee Update and Technical Excellence Award <details>

Playing Paula Abdul at the Denial (sic) Party.

Wednesday

BREAKFAST: Raiders of the Locked Art: Opening the Treasure with Interoperable PDK <details>

BREAKFAST: Accellera’s “Save Money Now! How to Reduce Costs, Complexity and Time to Market” <details>

LUNCH: Eclypse low power solution: First to Market with Differentiated Green-by-Design Electronic Consumer Products <details>

Connecting with industry bloggers at the blogger Birds-of-a-Feather session.

Thursday

PAVILION PANEL: Negotiating a Successful Career <details>

Friday

TUTORIAL: Low power techniques for SoC design <details>

I’ll miss a lot of interesting events, good technical sessions, keynote speeches, and calories.  But most of all, I will miss seeing all of my colleagues and friends.

Have a wonderful DAC, everyone!
EDA standards blog The Standards Game
DAC Design Automation Conference
VMM Verification Methodology Manual open verification methodology
UPF Unified Power Format low power design
IPL Interoperable PDK Library pcells
Women in Design Automation

It is with pleasure and a measure of pride that I’m letting everyone know that  Synopsys’ VMM verification methodology is now available via open source under Apache 2.0. We have heard numerous requests for our VMM implementation to be made open source, and today we have done just that.  And more.  VMM is as open as it gets.

In addition to the source code for our complete VMM implementation, we have also added a variety of resources to support everyone using or planning to use the VMM verification methodology.  All materials and resources are available now for free download at VMM Central including:

Source code for Synopsys’ complete implementation of VMM:

• VMM Standard Library
• VMM Register Abstraction Layer application
• VMM Reusable Environment Composition application
• VMM Memory Allocation Manager application
• VMM Hardware Abstraction Layer application
• VMM Data Stream Scoreboard application
• VMM Macro Library

Other resources to help improve productivity for both new and existing VMM users, such as:

• Documentation for the VMM Standard Library and VMM Applications
• VMM utilities, including RALGEN and VMMGEN, for rapid environment development
• Example VMM environments
• HVP verification planning language specification
• User papers and technical articles
• VMM user discussion forum
• “Verification Martial Arts” blog by Janick Bergeron, Synopsys fellow and co-author of the Verification Methodology Manual for SystemVerilog

I encourage everyone - customers, partners, and competitors alike - to visit VMM Central, download materials, and join the discussion group.

What does this mean to Accellera?  Simply that the donation we made to them of Synopsys’ VMM implementation is now available to everyone, inside and outside of Accellera.  While the Accellera technical subcommittee works on its formal standard(s) for verification IP interoperability, our customers, partners, and competitors can freely use and share VMM throughout the industry. 

It also means that portions of our original donation made to Accellera that were rejected by Mentor Graphics (which we were forced to remove) are now completely available to Accellera anyway.  Mentor Graphics has said they “can’t wait to get their copy of VMM”.  Now they can without any restrictions (and without complaints).

There are some unique aspects to VMM open source.  First, no registration is required to download the VMM implementation source code (unlike OVM).  Second, powerful utilities are available to augment the user’s deployment of VMM (unlike OVM).  Third, VMM has been used widely in industry on hundreds of projects by numerous customers and partners for years (unlike OVM).

Why is there any kind of license at all?  Because some companies don’t feel comfortable even looking at technology that was developed by someone else for fear of “pollution”, “tainting”, and other ominous perceived consequences.  (Which I think is silly - Synopsys donates technology, makes a public announcement, then somehow is going to file suit against users of the donation?  That doesn’t compute.)  The Apache 2.0 license is about the most flexible on planet earth.  It clearly spells out the rights given to anyone who accepts the license.  Among other things, users get the right to use VMM without restriction or requirement to report back to Synopsys, Accellera, or anyone else.  The only requirement is to keep the existing copyright statements in any VMM code that is not modified in a derivative work.

Speaking of derivative works, we have no intention of forking the VMM implementation away from the Accellera donation.  We will certainly stay closely involved in Accellera’s work - indeed, some of our top experts are active participants in the working group.  If there are future updates to VMM, the Accellera technical subcommittee will be able to obtain them immediately or at their scheduling discretion with no further ado.  

The VMM verification methodology is a structured approach to verifying complex system-on-chip electronic designs that significantly improves verification test coverage and minimizes the number of costly chip re-spins due to undetected functional errors while reducing test development time. By releasing the source code for the complete VMM verification methodology under the familiar Apache 2.0 open source licensing model, Synopsys is making this proven methodology easily accessible to verification engineers worldwide under simple, well-recognized terms.

Synopsys has again shown that we champion the cause of interoperability. From the Verification Methodology Manual book that anyone can buy, to our donation to the Accellera technical subcommittee which anyone can join, to open source via Apache 2.0, VMM is open.  Q.E.D.

EDA standards blog The Standards Game
verification methodology manual open verification methodology
VMM OVM open standard verification standard
open source open source standards Apache 2.0 Apache license

Sung very loosely to the tune of “Breakfast at Tiffany’s”: 

You say we’ve got no pdks in common,
No common ground to start from,
And we’re locked to one vendor.

You’ll say the world has to change between us.
Our pcells have come between us,
But I know you just don’t know about IPL.

And I say “What about breakfast at DAC?”
The theme is “Raiders of the Locked Art:
Opening the Treasure with Interoperable PDKs”.

You say, “I think I remember the film,
And as I recall, I think, we all kinda liked it.”
And I say, “IPL, it’s a good thing we’ve got.”

Register now (it’s free) at:

Interoperability Breakfast

And be sure to stop by Synopsys’ Standards booth to see IPL, UPF, and VMM.
EDA standards blog The Standards Game
DAC 2008 Design Automation Conference
IPL Interoperable PDK Libraries

As a mere mortal, I’ve decided that my 10 Commandments for Effective Standards can have “dot” commandments.  I’m introducing the 3rd.1 commandment: Know when to start.  I want to give credit to Gabe Moretti for the 3rd.1 commandment as he recently commented on my first 3 commandments in his blog.  My version of “Know when to start” adds an additional concept. 

There is a proper time to start a standardization effort for a technology (or format, API, database, …).  Before standardizing, it has to have reached a certain level of maturity.  Parents don’t send an ovum to school, instead they wait until the child has developed enough to get along with others, pay attention, and follow instructions. 

In our industry, the maturity of an EDA technology comes through customer usage in real IC design projects.  Subsequently, donations of proven technology to an experienced standards development organization (SDO) is quite effective as evidenced by Verilog, VHDL, SystemVerilog, Liberty, SystemC, UPF, and many others.  The final step is when the SDO transfers the completed standard to the venerable IEEE Standards Association for its formal ratification and moniker. 

Overall, the quality and merit of a standard relies on it having been deployed in the “real world” with a good measure of acceptance before sending it off to the graduate school known as the IEEE-SA.

Yesterday, Synopsys announced that the ever-popular Liberty format for library modeling has moved from the auspices of Si2 (Silicon Integration Initiative) to the IEEE’s ISTO (Industry Standards and Technology Organization).  In its new home, the Liberty Technical Advisory Board (LTAB) which oversees the format’s evolution will be able to include more members and ensure that Liberty can serve the needs of the IC design community for future generations of technology.  Not only have Magma Design Automation and Mentor Graphics joined the LTAB, but so has a major foundry.

It’s rather nostalgic for me to look back at how the Liberty format has moved through its standardization paradigms. As a leader in the electronic design automation industry, Synopsys strives to make the necessary EDA standards available through the most effective standardization processes and organizations (which keeps me quite busy, I must say).

When I first joined Synopsys 13 years ago, our library format – known as “.lib” back then – was a closed, proprietary format.  The format was developed around 20 years ago as part of Synopsys’ original product offering, Design Compiler for logic synthesis. It was a Synopsys-only format for 10 years or so.

Customers began experiencing the need for an open library modeling standard as they built design systems with tools from various vendors as well as their own homegrown special-purpose applications. The first step by Synopsys towards making .lib accessible to other EDA companies was via an open, company licensing model.  Anyone could use the format after obtaining a license from Synopsys.  Many companies took advantage of the opportunity to license and use our library format.

One day, my manager walked into my office and said, “Karen, I want you to open source .lib.”  I thought he was crazy – EDA formats were simply not made open source.  That was for operating systems and software.  Yet, it didn’t take us long to recognize that this revolutionary way of standardization would be useful (not to mention fast – back then, EDA format standardization was notoriously slow) for our customers and other EDA suppliers. Renamed “Liberty”, our library format was made available to everyone who used a “click-through” GPL-based license.  Downloads of the Liberty format soared, and the method of creating EDA standards through open source was launched in the industry.

After about 6 years of Synopsys overseeing the evolution of Liberty, we moved it into an Si2 coalition called the Liberty TAB (Technical Advisory Board).  There were 12 founding member companies of the board who directed enhancements of the format which was still available by means of its open source license.

Liberty stayed with Si2 for 2 years and has now moved to the next stage in modern standardization.  Under the IEEE ISTO, the Liberty TAB will enjoy another level of freedom (excuse the pun) in evolving the popular standard.  Liberty remains available through open source to everyone and continues to be the most widely-used library format in the semiconductor industry.

Not only has the Liberty format itself been improved over the years, but so has the process in which it is standardized. 

The Accellera VIP TSC (Verification IP Technical Subcommittee) is now up and running, with its charter to “define standard technology and/or methods to realize a modular, scalable and reusable generic verification environment”. The group is open to anyone who wishes to participate. Visit the VIP TSC website to sign up.

In support of this important verification standards effort, Synopsys has made a significant donation to Accellera. We have donated our complete Verification Methodology Manual (VMM) implementation source code consisting of:

• VMM Standard Library
• VMM Register Abstraction Layer application
• VMM Reusable Environment Composition application
• VMM Memory Allocation Manager application
• VMM Hardware Abstraction Layer application
• VMM Data Stream Scoreboard application
• VMM Macro Library

The Accellera committee can now take advantage of the years of investment in the VMM methodology made not only by Synopsys, but also our partners and customers, to produce a standard or standards which benefit everyone.

There is a real need for standardization in the area of verification, which I talk more about in my opinion piece in SCDsource. Not only can the Accellera VIP TSC create a valuable standard, but it can also deliver a unified solution that customers need.

EDA standards blog The Standards Game
VMM OVM open standards verification standards
verification methodology manual open verification methodology
Accellera VIP TSC

Over the years, I have gone through a lot of baggage.  (I’m talking about luggage, not the emotional kind.)  I have become a loyal customer of Briggs & Riley, and I won’t buy any other brand of travel bags.  Why?  Because of their guarantee. 

Briggs & Riley will fix any bag they make for its lifetime, even if the airlines damage it!  Their guarantee also covers normal wear and tear – really!  I’ve sent my bags to them at least three times for repairs, so I can attest that they cheerfully honor their guarantee.

What I find even more remarkable than their guarantee is an underlying reason for why they offer it.  Obviously, it builds customer devotion, but it also provides an opportunity for Briggs & Riley engineers to continuously improve their products. 

When a broken bag comes in for repair, they analyze what happened and figure out how to prevent the same kind of damage from occurring in their next generation of bags.  Over time, their bags have become more and more durable, saving them repair costs and saving their customers from having to replace bags as frequently.

It’s a business model that seems to work well.  I wonder if there’s a way to apply it to standards.

EDA standards blog
The Standards Game
briggs & riley briggs and riley baggage luggage

It’s always exciting when a new standard activity launches.  There’s hope and expectations for a solution that will greatly help improve productivity for customers and suppliers alike.  I don’t have statistics on how many new standards are ultimately successful.  That would be some interesting data.

I do know that not every standard that starts becomes completed and adopted.  Completion - the official ratification by an organization or managing entity - is important, of course.  Yet it’s adoption that indicates the true measure of success for a standard.  The number of customers using it and the number of tools that support it are the best indicators of a viable standard.

There are dozens of EDA standards sitting on the shelf unused.  (Remember VHDL Waves?)  Resources consumed by these standards could certainly have been better spent. Working on a standard that isn’t going anywhere is a senseless waste.  If there is a well-adopted standard that is available to everyone, it is not effective to create a competing or overlapping one.

Hence, my 3^rd Commandment for Effective Standards is: Know when to stop.

No one likes to admit defeat, but shutting down an ineffective standards activity is only right.  If an already-accepted standard is made available to everyone, it’s important to stop working on an alternative. 

The EDA industry has done this at least three times in standards for libraries, constraint languages, and physical description languages. Let’s hope this commandment continues to be honored for many years to come.

EDA standards blog
The Standards Game