I think it’s fun to write blog posts during a conference. In addition to giving highlights from presentations, I try to capture interesting comments that speakers make which aren’t on their slides and human interest stories that happen during the event. Here’s my eye witness account from Synopsys’ 22nd EDA Interoperability Forum. (That’s me in the photo, making the opening remarks.)

We continued our playful theme of “Peace, Love and Interoperability” for the Forum.Titles of presentations included “Flower (Low) Power”, “Make (Verification) Plans, Not War”. and “Turn on! Tune in! Tape Out!”. Presentations will be available on our website after November 13, along with presentations from past Forums.

Several people wore tie-dyed shirts to the Forum and made jokes about how much hair we all had in the ‘60s. I saw some new faces and many dedicated interoperability practitioners who attend the Forum regularly. Synopsys purchased carbon offsets in a step towards a sustainable Earth. A gentleman from Jasper won a backpack full of prizes, and the lunch buffet was tasty and nutritious. There was a bit of action on Twitter as well – search the hashtags #EIF22, #snps and #EDA to see some of the tweets.

Subodh Bapat, VP of Energy Efficiency at Sun Microsystems, delivered quite an interesting keynote about data center power consumption. (It will be the topic of my next post as this one is getting too long.)

The first speaker was Rajesh Kumar from Synopsys who gave an update on the Liberty library modeling standard. One of the key benefits the Interoperability Forum provides is insights into standards like Liberty that give EDA suppliers a head-start in developing interoperable tools.

Neil Songcuan, also from Synopsys, talked about the HAPsTrak standard input/output  connector that’s mounted on the HAPS rapid-prototyping board. Essentially all SoCs use some kind of rapid prototyping, and the standard I/O connector makes rapid prototyping easily deployable, promotes reusable hardware for future projects, and minimizes risk. This is the first time that the Forum featured a standard that’s actual hardware.

Richard Paw represented the EDA Consortium’s OS Roadmap Committee. This group produces guidelines for operating system and hardware platforms that help unify EDA tool support around common platforms. (It drives customers crazy when the tools they purchase don’t support the same platforms.) The guidelines will be updated in September 2010. Added will be SLES 11 (SuSe Linux) and Windows 7. Dropped will be SLES 10. In 6 months, the committee will review Windows XP, Vista, and the upcoming RHEL 6 (RedHat Enterprise Linux).

Dave Graubart represented the EDA Consortium’s Anti-Piracy Committee. He said it’s hard to feel the love when you’re getting ripped off. The committee estimates that 1/3 of all EDA software use worldwide is pirated or overused beyond the license agreements. Not scientific data, but troubling nevertheless for the EDA industry. It’s easy to find the stolen binaries so most of the 1/3 estimate comes from this, not misuse/overuse which is harder to find. There are potential techniques to help prevent this piracy and the committee will continue its work to solve the problem.

Cary Chin from Synopsys presented the current state of the 1801 standard, which was approved as an IEEE standard in March 2009. I’ve written a lot about this standard, and I’m relieved to see evidence of convergence – or at least interoperability – with the Si2/Cadence CPF (Common Power Format).

Ed Lechner, also from Synopsys, gave an update on the IPL Alliance which began 2.5 years ago. Users are proving out the standard which is based on OpenAccess and provides the industry with a means to create and employ interoperable PDKs (physical design kits). An interesting discussion followed Ed’s presentation about whether IPL Alliance members would provide 180 or 130nm offerings. The IPL Alliance has focused thus far on 65nm and smaller technology, yet one audience member contended that the analog/mixed-signal world is still at 250 or 350nm. Customer members will be able to bring their larger geometry demands, if needed, to the IPL Alliance.

One of the most interesting sessions at the Forum was a live, international demo of an interoperable PDK in use. 10 tools from 5 vendors were run using a single, interoperable PDK and a single OpenAccess database – with no data translation! “Far out, man,” was the introduction from SpringSoft which kicked off the demo (pictured here).

Frank Schirrmeister of Synopsys described the System-Level Catalyst program which accelerates the adoption of system-level design and verification. Among other benefits, program members receive access to Synopsys’ system-level and rapid prototyping products for interoperability development. A hardware/software interface can have lots of bugs, so system-level design and verification is a necessary step in the development process. As Frank stated, in a system it’s the software that’s the differentiator. And so is the hardware (depending on your point of view).

Dr. Andrea Kroll from JEDA Technologies spoke about automating model verification. Model developers can spend 30-40% of their time in verification, then the consumer of the model can spend the same amount (or more) verifying the model before using it. The standard TLM 2.0 model interoperability (a set of API calls, modeling styles, and rules) comes to the rescue.

Bill Neifert, founder of Carbon Design Systems (system-level modeling & validation tools), talked about validating complex software on a new hardware design. He showed a “virtual system lifecycle” starting with model generation and ending with model deployment.

Grant Martin from Tensilica talked about their ESL methodology and ISS-Innovator integration. (I remember working on Accellera’s policies and procedures with Grant a few years ago. I’m guessing he likes working on ESL more than P&Ps.) In the future, TLM 2.0 should be standardized via the IEEE 1666 working group. Grant suggested some improvements that could be made to the standard, and said Tensilica is happy to help. That’s the spirit I admire.

Robert Freeman from Synopsys said, “It’s all groovy with VMM 1.2”. He explained that a methodology is essential for significantly reducing the time needed to complete verification while finding the challenging, “strange” bugs. (In the old days, we knew that verification was finished by looking at the calendar, not by looking at the coverage.) Since a few people in the audience weren’t familiar with VMM, it was good that Robert talked again about VMMCentral and its resources.

Mark Gogolewski of Denali emphasized the important of verification planning because verification is incredibly expensive and time-consuming. He gave a practical description of how to do planning with Denali’s tools and Synopsys’ VMM Planner.  An audience member asked how flexible is the VMM planner for different architectures. Mark answered that he doesn’t write code any more (nor do I, for that matter), but his customers and engineering teams say it’s extremely contemporary, so  he’s confident that it’s flexible. Another question for Mark was how well does the VMM planner calibrate coverage, i.e., how intelligent is it? He explained that it’s dependent on the coverage library you define, and it’s an advantage of VMM because companies offer verification IP now that can be dropped in quickly. Plus, the VMM planner does quite a capable job moving through the data.

John Goodenough from ARM talked about VMM for Low Power, focusing on aspects that make standards like VMM happen to the benefit of industry. As VMM has done, engagement across the industry is required, not just with 1 or 2 players. (I’d say that ARM’s ecosystem is witness to John’s wisdom.) He also mentioned that electronic devices today need to operate in the lowest power mode possible not only for battery life, but also to be green.

Ambar Sarkar of Paradigm Works said there’s a tremendous amount of code required to reach the registers in a chip for verification. Home grown solutions have issues. With the RAL application – part of  the VMM standard – these issues are mitigated. Paradigm Works will make their implementation available on SourceForge.

Doug Smith of Doulos give some source code and examples of the new features of VMM 1.2. (Thanks to Doulos for providing each Forum attendee with a free copy of their VMM Golden Reference Guide.) As part of the beta program for VMM, Doug learned first-hand about these features and providing his technical expertise to the Forum audience again demonstrated the value of the Forum to its attendees.

The 23rd EDA Interoperability Forum will be held in Fall 2010. We’ll work hard again to bring solid value to everyone in the standards game.