I know it sounds funny, but I’d been anxiously awaiting a press release. A new standard had been ratified by Accellera, the premier standards-setting organization in my industry of chip design automation. So as not to steal their show, I had to wait until their press release came out to share the good news.

Accellera’s working group, the Verification IP Technical Subcommittee (VIP-TSC), has completed the first of 2 milestones it set out to accomplish. The working group began about a year and a half ago, and I was optimistic that they would do a good job. They decided to divide the task of producing a verification standard into 2 parts, a “short term” and a “long term”.

Their “short term” standard is now complete and is called “Best Practices Interoperability Guide”. This document provides information about using SystemVerilog verification components in an interoperable testbench environment, and it includes a reference library. It supports both the Verification Methodology Manual (VMM) and the Open Verification Methodology (OVM) which should make everyone happy in the standards game.

Now it’s time for the group to start working on their “long term” standard. Their efforts will produce a common base class library that can be used in simulators from multiple design automation tool vendors. The common base class library will foster a broad (universal) verification methodology to benefit verification engineers and developers of verification IP.

Again I’m optimistic that the VIP-TSC will provide the industry with an effective verification standard. Hmm. Maybe they will call it the Universal Verification Methodology (UVM).