You could say I’m nuts about 1801. I’ve written about this standard for low power design many times, such as its open environment within IEEE and Accellera, the fact that users and vendors alike developed it, and how real customers have been using it as a successful, working standard. From the day that two leading customers of EDA began a rally around “open, quick, inclusive”, to the creation of the Unified Power Format (UPF) in Accellera, to its finalization as an IEEE standard, I’ve felt it took the right direction in EDA interoperability.

In a nutshell, here’s why:

• It allows flexibility in creating power strategies without forcing customers into a pre-defined flow.
• It permits choice by users. For those who want a single file to contain their IC’s power intent, 1801 works. For those who want power intent constructs in their RTL, 1801 works.
• It augments multiple existing standards such as Verilog, SDC design constraints, and Liberty. It didn’t make sense to reinvent the wheel and make IC engineers retool. Interoperability is served well when current standards are leveraged.
• It offers support for legacy designs. Low power chip design didn’t start after low power standards were born. (Quite the opposite.) Being able to continue using existing code and methodologies can help designers reduce errors and increase productivity.
• It enables different EDA vendors to develop unique solutions, following the 1st Commandment for Effective Standards: cooperate on standards, compete on tools.

In the near future, the IEEE process for ensuring healthy standards will bring about the next 1801 project. When this happens, I’ll post information about how everyone can participate in the P1801 working group.