Twitter is a fascinating social media tool, and several of us used it during DVCon. Rather than a  traditional narrative about what I saw and did at the conference, I thought it would be interesting to capture my tweets that I posted throughout the conference. Let me know if you love or hate it. You can find all the DVCon tweets various ways with a search.  (If you’re curious about Twitter, I’d enjoy sharing what I’ve learned about it.)

In looking over what I sent to the Twittersphere, I realized I was worried about the attendance at DVCon (lots of head-counting in the tweets) due to the economy. I was relieved to see the sessions fairly full and happy that the attendees seemed engaged and getting value from the conference. And I was delighted when some of the #DVCon Twitter followers who couldn’t attend the event said:

@karenbartleson, @jlgray, very impressive tweeting – I feel like I am at #dvcon!

Going to bed after a very long day at a client. Looking forward to DVCon updates tomorrow.

@jlgray @karenbartleson I need a 12sec vid so I can feel like I’m @ #dvcon I am sitting here with corny badge holder around my neck waiting

Thx for all the conference twittering. It’s almost as if I was there this week. No, not quite.

@jlgray, @karenbartleson, bravo! Nicely twittered. I enjoyed that – #dvcon

Now, here’s a stream-of-consciousness snapshot from karenbartleson via Twitter:

Day 1

I’ll say this once so i don’t repeat myself the next 3 days at #DVCon. All my tweets are my own humble opinions.

#dvcon tutorials on VMM and OVM have decent attendance – roughly 50-60 each. Encouraging.

Synopsys announced the VMM-LP at #DVCon. It’s our low-power verification methodology manual with ARM and Renesas. http://tinyurl.com/bhddgm

in Mentor’s #DVCon tutorial, Fitz is educating audience about UPF, the Unified Power Format for low power design.

papers at #DVCon are reviewed blindly and accepted for their technical merit.

at Accellera lunch at #DVCon, Shrenik asked the nice-sized audience if they are familiar with Accelllera. Almost all said yes!

Karen Pieper, Accellera’s technical committee chair, gave an update on Accellera’s standards. I found it impressive.

#DVCon Steve Bailey, chair of P1801 – UPF 2.0 is giving an overview. The working group worked hard.

#DVCon UCIS committee is reviewing donations from Synopsys and Mentor.

#DVCon Results of the Accellera OVL survey had >100 responses, >half users, 70% use ABV, SystemVerilog much more than others

#DVCon Sri Chandra wins Accellera technical achievement award for Verilog AMS. Congrats, Sri!

#DVCon is definitely the right venue for the annual Accellera member meeting.

If you’re waiting for me to talk about VMM vs. OVM at #dvcon, don’t hold your breath. Ain’t gonna do it. Wouldn’t be prudent.

approx. 45 people in Cadence’s OVM tutorial at #dvcon.

@newtechpress try searching for #dvcon. you’ll see individuals twittering.

I’m at the exhibits at #DVCon. There are a lot of people here.

Day 2

#dvcon bkfst. Ken McElvain talking about s/w content of SoCs. Looks like some attendees didn’t set their alarms. But good Q&A.

#dvcon Opening remarks by Tom Fitzpatrick, General Chair: 150 people at tutorials. >600 attendees year. Remarkable in this economy.

Twittering helps the social networking at #dvcon as well as the technical networking, per Fitz.

IEEE-SA being recognized at #dvcon opening remarks.

Ambar Sarkar, Technical Program Chair of #dvcon gave stats: 9 panels proposed, 117 abstracts submitted (8% increase), new sessions added.

eating Cadence lunch at #dvcon. another nice-sized audience. listening to OVM a few OVM case studies.

@dennisbrophy The new corporate dues model is a major step forward. Everyone attending #dvcon has an opportunity to benefit. Well done!

oops! The #dvcon speaker from Sirf just called CPF the Cadence Power Format.

the large audience at Aart de Geus’ keynote at #dvcon is engaged and enjoying his talk quite a bit.

#dvcon Aart says that 65nm ICs are half hardware, half software and software content is increasing. Guess what is in all of our futures?

#dvcon The next wave of IC design will be System Prototyping which is virtual prototyping + rapid prototyping + IP.

Shrenik Mehta, Accellera Chair, awarded Accellera’s Technical Excellence Award to Sri Chandra from Freescale for Verilog-AMS work. #dvcon

Karen Pieper, Accellera’s Technical Committee Chair, accepted the award for him. He was on the phone in India! #dvcon

Peggy Aycinena is now moderating the exec panel at #dvcon, formerly done by John Cooley for years.

#dvcon exec panel abstract and lineup are here http://www.dvcon.com/html/panel1.html

#dvcon Peggy asked "Is EDA press dead or alive?", said maybe they’re chars on a tweet or sponsored articles – not journalism, but oh well.

I think I’ll tell Peggy at #dvcon that bloggers & twitterers like @jlgray, @harrytheasicguy, & me are members of the "Civilian Press Corps"

#dvcon Ajay Bose, Atrenta: EDA is not dead because if it were, semiconductors would be dead and that’s not going to happen.

I now have the raw material for a short film from #dvcon "The Blair Witch EDA Panel".

I admit that I don’t have enough SIADD http://tinyurl.com/dymdgj to tweet and flip video simultaneously at #dvcon.

maybe solving system-level design and hw/sw design issues will ensure that EDA isn’t dead. #dvcon

oh dear, here come the commercials at the #dvcon exec panel. i hope the customers like them.

Regardless of the "official" survey results, I like it better than the past Cooley panels. My informal Twitter vote.

OMG. Are the old EDA people supposed to die now? The #dvcon panel is taking a depressing turn.

#dvcon peggy just asked what the eda companies are doing for universities. snps has a big program (it’s mine).

doing my own tools would mean no interoperability problems? i don’t agree. design data would still flow between tools w/buggy i/fs. #dvcon

yes, peggy, as an employee of an eda vendor, i am working as hard as i can for my customers. #dvcon

#dvcon for the 7 panelists, on your roadmap?: cad for biology 0; carbon nanotubes 0; cloud computing 3; multicore/threading 6

#dvcon gabe challenged the eda industry to think beyond semiconductor company probs they hand us today and solve their probs of the future.

#dvcon SaaS session, just now got connection/computer working (blackberry out of service all day). missed tweeting it, now Q&A going on.

#dvcon SaaS session: discussion on behavior changes and license model changes.

#dvcon I think Harry is recording the audio. Peggy is here. Richard Goering is here. Should get some good info from them post-event.

a well-known VHDL expert, @thenextwriter, published a thriller/adventure novel. can’t wait to read "Lost in the Sky" by Douglas Perry.

Day 3

just came from the #dvcon steering committee meeting. i will have a special role next year.

Eating Mentor’s risky business lunch at #dvcon. Fortunately, Steve Bailey is not in his underwear dancing to Bob Seger.

#dvcon session 11 low power mgmt. About 25 attendees. OVM/CPF VMM/UPF. Ah, the standards game. http://www.synopsysoc.org/thestandardsgame

#dvcon Gary Delp talking about 1801 aka UPF standard. I always like to hear him speak. He has 45 patents! I’m not worthy.

#dvcon TI’s Freddy Brembaron is presenting a UPF example. Like Gary Delp from LSI, it’s great to hear real users talk about UPF (1801).

#dvcon panel on mixing formal verification and simulation. About 60-70 attendees.

#dvcon panel on mixing formal verification & simulation. ~75 attendees. Tools are easy to use, Methodology is hard.Audience very engaged.

#dvcon attendees voted. Best paper award & $1K went to 11.3 Low Power Verification Methodology using UPF. Texas Instruments & Mentor.