I’m prompted to write this having read Jim Lipman’s account of the DAC roundtable on “Can IP Integration be an SoC Methodology or is it Always Ad-Hoc?” where I was a panelist. Essentially Jim’s take on the roundtable was that IP integration is not a slam dunk. This is the opposite of what I actually said…Here’s my response to Jim.

My viewpoint is contrary to your summary! What I said at the roundtable was that it is possible for third-party IP integration to be - using your expression - “a turnkey operation”. I said that the dependencies were on the type of IP, completeness of the IP deliverables, thoroughness of the IP design methodology and the expertise of the IP design team. The last two points are not so apparent until you actually engage with the vendor.

Starting with the “type of IP”, I was at pains to highlight the differences of  non-standards based IP such as PLL’s and data converters, stating that  there is no standard spec and the integration deliverables need to be modified depending on SoC interface. This is where you cited the VSIA as being a potential solution and I countered that each of these blocks is application dependant making the job of creating a standard checklist onerous.

Using PCI Express as an example of standards based IP, my point was that even though it is a very complex protocol from the digital link layer to the serdes based PHY, the IP can be designed such that it can be integrated by an engineer that is not an expert in the protocol or in mixed-signal. What a good third party vendor does, in order to make the IP drop-in, is to provide all the design views including detailed integration guidelines. I spoke about the different lane configurations that are supported in PCI Express (x1, x4, x8) and that the IP deliverables must be targeted for these different lane counts.

The methodology used to create the IP deliverables is also very important and at this point we spoke about test-chips, compliance workshops, split lots to see the impact of process shifts on performance and silicon characterization. I added that good IP vendors must also provide support for ESD and latch-up protection.

In terms of the IP design team’s expertise, the most important criteria is that the IP must be designed like the rest of the (predominantly) digital SoC, in a bulk CMOS technology, no special process options for on-chip inductors, for example. Designers building IP for SoC integration such as a SATA PHY, face different challenges to the designers of discrete SATA chips. I made the assertion that the discrete designer may not necessarily design good IP. Power, area, ease of integration, and production testability are the key care-abouts of the IP designer whereas the discrete designer is focused on performance.

I also said that we cannot control where customers place the IP on their chips, and spoke about the IP design methodology – essentially what we do before we ship IP to customers. At Synopsys our test-chips have noise generators around the IP to ensure robustness in a harsh digital SoC environment.

Making the IP easy to integration is only part of the story. If you now have PCI Express on your chip how do you test it? To this I said that we provide on-chip diagnostics and test vectors that enable our customers to do production testing using a conventional digital tester, eliminating the overhead of writing the test-program.

I concluded by saying that good third party IP vendors have a roadmap aligned to their customer’s future needs, for example at Synopsys we do this by working on the standards bodies like PCI-SIG and USB IF for the next protocols generations and the foundries for the latest technology directions. Today we’re offering a number of very powerful silicon proven IP building blocks and customers now have at their finger tips the ability to build systems-on-chip, the system engineering task is becoming more complex, but also offering more room for differentiation.

I’m very optimistic about the future!
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A busy week, this week for mixed-signal IP. Leaving for Anaheim early Monday morning for DAC and then returning for PCI-SIG Developer’s Conference later in the week. Just completed the finsihing touches for the tutorial on  “Advanced Methodologies in Validating and Integrating High Speed Serial Interconnects in the Ultra Deep Sub-micron CMOS Era”, presented with Open Silicon on Tuesday afternoon. http://www.dac.com/events/eventdetails.aspx?id=77-144 for details. This is a “strictly for designers” tutorial.

Also during the DAC week you can see a PCIe 2.0 PHY silicon demo at the Common Platform booth, feel free to come over and ask me any questions, I’ll be pleased to show you some of the exciting features like the the built-in diagnostics showing the received eye at 5Gb/s.

Before heading back for the PCI-SIG Developer’s Conference, I’ll be participating on an IP Roundtable Breakfast – Wednesday, 8AM at the Hilton Hotel: “Can IP Integration be an SoC methodology or is it always ad hoc”.

For the PCI-SIG DevCon, we’ll have demo of the PCIe 2.0 PHY and on June 12th will give a talk on: “Designing High Speed Transceivers for PCIe 2.0 and Beyond”