In my last posting I introducted the challenges of meeting signal integrity requirements in wirebond packages for high speed DDR interfaces. Perhaps more than any other wired interface, packaging decisions and careful PCB layout play a critical role in determining the success or failure of a DDR interface especially for DDR3 at 2133 Mb/s. Unlike the PCI Express, SATA and USB PHY’s there is no standard or compliance stipulations for the DDR channel.  Poor power delivery characteristics can lead to effects from simultaneously switching outputs (SSO) that slow down the circuitry and distort waveforms leading to timing margin erosion.  

DDR interfaces highlight SSO impact since the DDR Controller/PHY in the SoC launches the source synchronous data strobe 90 degrees out of phase with the data (also called “center aligned” since the DDR PHY must launch the data with the data strobe centered in the data eye), but the DDR SDRAM launches the data and the data strobe in phase (also called “edge aligned”) since the DDR SDRAM launches the data and the data strobe at the same time. This leaves the DDR PHY responsible for phase shifting the data strobe into the center of the data eye before it is used for data capture within the DDR PHY). Below you can see this in action from one of our DDR3 PHY’s:

Figure showing Synopsys’ DDR3 at 2133 Mb/s with a centered DQ eye between the AC thresholds

The result is that during writes from the controller/PHY on the SoC, data signals can be delayed by SSO effects but the data strobe signals, which are shifted in time, are much less impacted by the simultaneously switching data, introducing unwanted data to strobe skew that that disrupts the 90 degrees phase relationship and erodes the timing budget.  Since reads launched by the DDR SDRAM are in phase, the SSO delay affects the data and data strobe equally, introducing a minimum of skew. 

The next posting will describe some of the differences between single ended versus differential strobes.