In the last couple of postings I discussed technology scaling and it’s impact on analog IP.  The point is that like digital gates, analog IP benefits from technology scaling  but with a very different methodology – not using design tools but using different analog architectures: http://synopsysoc.org/theeyeshaveit/?p=242 illustrated USB 2.0 PHY scaling from 180 nm to 28 nm and http://synopsysoc.org/theeyeshaveit/?p=273 showed the example of a dual 10-bit, 80 MHz ADC in an 180 nm technology being five times smaller in 65 nm. So, if we go below 32/28 nm, will we continue to see this size reduction in analog IP?

Is there a size limit?

Our conjecture is that area improvements will happen, but not at the dramatic level as in the 180 nm to 65 nm example above. A couple of reasons for this:

• The advantages of moving from I/O devices to core devices has already been achieved with 65 nm technologies. Moving forward it will become harder and harder to design using sub-1V supplies and the designs will become more complicated in order to yield good performance at those low voltages. Most likely there will be only two transistors stacked with many more placed laterally. 
• The converters are now a very small fraction of the complete SoC area, even if, in some cases, multiple instantiations of the converter are used (for example, MIMO transceivers). Therefore there maybe no market driver/need

Of course, I’m saying this from today’s perspective. With new structures like finFET’s area and power may be further reduced.