Unlike digital transistors, scaling does not happen so readily or cleanly with analog blocks. The motivation to scale is driven by the fact that digital transistors scale quadratically with each process generation. There are many reasons that analog does not scale as readily. Mostly this is related to the fact the the I/O devices and passives, typically used extensively in analog circuits, do not scale from node to node.  So, is there any hope in benefiting from the process node scaling that we see in digital transistors?

The diagram above shows three generations Synopsys’ USB 2.0 PHY. As you can see we have managed to scale the design from the original 180 nm to today’s 28 nm version. Getting there wasn’t as simple as re-targeting standard cell libraries, followed by running automatic place and route. Scaling was achieved for this analog/mixed-signal IP and this was done by number of different design techniques.

The parameterized transistors cells were technology node optimized and much of the high speed analog circuitry was pushed to the low voltage core domain. The smaller technology nodes do have a higher poly sheet resistance per unit area and this helps in making the resistors smaller as well. The I/O voltage also scales from 3.3V to 1.8 V in 28 nm – this provides benefits in more efficient capacitor designs making the low pass filter in the PLLs, for example, much smaller. Of course you need to make due consideration to leakage, linearity and breakdown voltages.

So scaling can happen in analog too – but it is more than a push button operation.

More information on Synopsys’ latest USB 2.0 PHY on http://synopsys.mediaroom.com/index.php?s=43&item=745