I was recently interviewed by Lee Goldberg on the launch of my latest product, the
PCIe 2.0 PHY. http://www.en-genius.net/site/zones/connectivityZONE/product_reviews/iop_050508

He has a nifty way of rating the interview on how many grains of salt should be taken with the manufacturers claims.

I got a comment on my last entry which said they used an on chip micro-controller to perform functions like VCO band selection; DC offset correction in receive path, on chip AGC.

 Expanding this you could also consider the following (Bart Dierickx, IMEC 2007):

Monitors: Delay monitors, CRC or parity checking, memory BIST, detection of noise margins, power supply or current sensing and local temperature sensors.

Knobs: Back biasing, VDD, speed versus power in drivers, speed/power/noise margin in line drivers, current biasing power/speed…

In the next post I’ll describe what we’re doing at Synopsys to monitor performance in 90 nm, 65 nm and 40/45 nm processes for high speed SERDES design.