So what’s the deal?  If you look at USB 2.0 connector it has 4 pins: Dplus, Dminus, GND and 5V. For an embedded USB 2.0 PHY, the 5 V must be supported on the semiconductor technology that the rest of the chip uses. Today this is 65 or even 40 nm with 2.5 V or 1.8 V oxide. So the challenge is to build a circuit that can support 5V using a transistor, in the case of 40 nm, that has been only been rated to 1.8 V.

This requirement together with all the other electrical specifications is documented by the USB Implementers Forum. A couple of months ago we took our first USB 2.0 PHY test-chip design on TSMC’s 40 nm process using 1.8 V native devices to the USB sanctioned testing lab. We ran the 5 V short tolerance test for the required 24 hours. We passed this test and met all the other electrical requirements - meaning that the USB 2.0 PHY is certified to meet all the electrical requirements including 5 V tolerance. http://synopsys.mediaroom.com/index.php?s=43&item=636

So the question is…how did we do it? Well, come to my tutorial at the next SNUG and all will be revealed. (Well not quite all…just enough!)

Analog/mixed-signal design on 45 nm was treated with some trepidation by one of the panelists at ICCAD last week: http://www.scdsource.com/article.php?id=319. See the section “45 nm? Don’t go there”. Contrary to the viewpoint of this panelist (who happens to be a friend and ex-colleague), it is possible to build robust high performance analog/mixed-signal on these leading edge digital CMOS technologies. And I have production silicon to prove my point! 

Let’s look at the differences between analog and digital design at 45 nm (and below). For digital design – the basic functionality scales. The NAND gate still looks the same. There is a significant density increase to allow you to do more – deal with more — but the devices, while tiny and fast, leak a lot, can’t be tunred off. And there is a lot of variation in timing. But in the end – most of the effort is focued on managing the power dissipated by all of the devices that aren’t doing anything. Plus the normal signal integrity and DFM concerns.

In analog design, the devices leak as well of course, they don’t perform as well as current sources, and there are physical reasons why it is difficult to make two devices identical. But some of the performance degradation due to the thinner gate oxide and smaller dimension can be mitigated by using the I/O device – the OLD analog transistor, if you will.

In this case you have to decide how to mix – higher voltage; lower voltage domains – trading off between the higher performance (speed) of thin gate deivces with the better precision of thick gate devices.

What becomes critical in the performance of analog design, is the sources of variation in the devices due to effects like shallow-trench isolation, well proximity, contact stress, phase shift mask correction algorithms, and then time dependent variation due to negative bias temperature instability in PMOS devices and hot carrier injection in NMOS devices. Once the impact of these are understood, you are well on your way of designing robust circuits in these advanced technology nodes.

Clearly, since the digital functionality scales so well – there is a huge advantage to moving everyting practical into the digital domain. For example, using a digitally controlled analog PLL. That means that the conventional PLL loop filter is implemented as a digital filter, a filter that now becomes insensitive to processing, voltage, and temperature.

It is also becoming necessary to have visibility into the analog domain so you can check the analog performance of internal circuits. I recently wrote about this topic: http://www.edn.com/article/CA6586230.html

Finally, it is common to use analog techniques to remove normal variation using feedback – the classic case of a PLL where variation in the period or frequency is removed by locking to a reference using a feedback loop.

So the bottomline is that analog on 45 nm (and below) is being successfully designed, it may not be for the “old school of analog designer”. In fact we are in the midst of developing high performance mixed-signal circuits on 28 nm.