There seem to be some confusion about types of checks that need to be performed on a Low Power Design. In the Low Power static check world, following 3 types of analysis can be done on a design, in addition to various other checks.

(a) Critique Check

    Power State Table is Golden here and design structure is validated for correctness based on this table. For example “ Compare the ISO/LS elements present in the design with the ISO/
LS requirement inferred by analyzing the PST”

(b) Power Intent Check

Design is validated as per the Power Intent provided by user, here Power State Is ignored and mostly user written rules/policies are considered while checking, design structure is validated against user written policies  for correctness.

(c) Low Power Architecture Checks

Here design is analyzed for any architectural failures with respect to the requirement specified in the power intent. For example: Checking Power Up and Power Down Sequences of various power domains, checking for reachability of control and clock paths to the design.

How do we minimize or reduce area in a Low Power Design, especially when it come down to using special cells such as isolation cells, level shifter cells…etc

Here is one scenario, where in “especially on a final sign-off netlist, can we get rid of these or will there be any electrical violations due to this”

Again this is after considering all the physical requirements, since these special cells are inserted very early in the design cycle, should we be visiting them again before signing off? Just a thought!