last week we saw physical structure of LS/ISO cells. Today lets look at

(a) Retention Registers: These are typically either dual height cells or single height wide cells. They have Primary Rail and Secondary Rail. Primary Rail is switchable and Secondary Rail supplies power, when Primary Rail is off. They are typically placed in a shut-down region. One important factor is, Secondary Rail need not be of same potential as Primary Rail in ON state. Having a potential just enough to retain the state while primary is off would be the most efficient way to optimize leakage. Higher the Secondary Rail potential more will be the standby leakage current.

One of the biggest challenge in the design process is how can we automatically identify, number of registers in the switchable block to be retained? This could be done primarily based on the design architecture knowledge and also based on how fast one wants the switchable block to be up and running. Latter part can be automated in a way using some of the formal/property checking tools.

Other challenge is in verifying the functionality of Retention Register during functional simulation. Some of the verification challenges are listed below.

(i) Simulate Save/Restore Functionality.
(ii) Verify the functionality of ” When Save is asserted Secondary Rail is already active with the required potential”.
(iii) Verify the functionality of ” When Restore is asserted Primary Rail is completely ON”.
(iv) When Retention Register is in Save mode and if Secondary Rail drops(because of adjust block waking up) to a value below the required potential, how do we recover ?
(v) What if Save/Restore Lines are not treated as ALWAYS_ON ?

……etc

Lets look at the the other 2 important cells in the next post.

Today let me give a quick insight into various special cells and their physical structure

(a) Level Shifters: In general there are 3 types of Level Shifter.

(i) High2Low LS: Shifts the Voltage from High 2 Low. Physically these are single row height cells and have 2 rails VDD and VSS. Conceptually they are nothing but high drive buffers and nodes gets charged upto the VDD(low), even though input is driven from higher voltage source. One of the key requirement for this kind of cell is they got to be placed in Lower Voltage Domains.

(ii) Low2High LS: Shifts the Voltage from low to high. Physically these are 2 row height cells and has 3 rails, Primary VDD(Low), Secondary VDD(High) and VSS(Ground). Ideally these are placed in Lower Voltage Domains.

(iii) Generic LS: These cells can shift the voltage in either direction. They are generally used in designs that deploy DVFS technique. Physically these are 2 row height cells.

(b) Isolation Cells: In general there are 3 types of Isolation cells.

(i) Simple Isolation Cells: Physically these are single height cells
(ii) Enable Level Shifters: These are combination of a Isolation cell and Level Shifter. Physically they are similar to level shifter explained above
(iii) AON Isolation cells: These are dual rail cells, physically these are 2 row height cells and has 3 rails, Primary VDD(ON/OFF VDD), Secondary VDD(AON VDD) and VSS(Ground)

I will discuss about the other special cell’s physical structure in my next post tommorrow.