I have worked in the VLSI industry for 14 years as a digital IC designer. My recent work has been focused on low-power challenges associated with multi-voltage/Vt Cells Spacing Requirements
Posted by Godwin Maben on March 31st, 2007
Multi-Vt placement/spacing concerns
I was just thinking about most common concerns faced today in addressing leakage power. Multi-Vt spacing requirement is something everyone faces as multi-vt has become more or less part of regular implementation flow, thought of sharing the same today.
What’s Multi-Vt?
In trying to meet the stringent leakage requirements, usage of Multi-Vt cells has become more or less must have. Let me give a small description of the same.
Balancing timing and leakage power requires the use of multiple libraries whose cells operate at different threshold voltages. Cells, which operate at higher threshold voltage are slower and less leaky, where as cells that operate at lower threshold voltage are faster and very leaky. Optimization engines meet timing goals by using the low-Vth cells on critical timing paths and high-Vth cells on non-critical paths. The low- and high-Vth cells have the same footprint for equivalent functions. Depending upon where you perform optimization in the flow, these cells are either just swapped (ECO) or paths are resynthesized (Synthesis/Placement) to meet timing/leakage goals.
Is it so simple?
Even though the above sound simple, it comes with its own implications that need to be addressed during chip finishing stage to meet certain process requirements.
Maintaining the same footprint requires careful library design because the low-Vth cells have a different well implant to create their lower threshold voltage. If this implant extended to the edges of the cell, it could overlap the edge of an adjacent high-Vth cell. The cells are therefore designed with a small buffer space around the edges, Low Vt and High Vt cells can be placed side by side. Figure 1/2 below demonstrates a simple scenario of Vt spacing requirements
Problems can occur if cells of the same Vth type are placed with a small space between them and a filler cell of the opposite Vth type is used to fill the gap. This mismatched filler creates a gap in the implant regions that violates design rules. Typically this problem is addressed by inserting filler cells intelligently.
How should I handle it?
Most of the current generation P&R tools like ICC/Astro will insert suitable filler cells next to the VT cells, when needed. Typically, filler cells are used to fill any spaces between regular library cells to avoid planarity problems and provide electrical continuity for power and ground. Because the High Vt cells have a different diffusion layer over them, a High Vt filler cell needs to be placed between High Vt cells, and a Low Vt filler cell needs to be placed between Low Vt cells.
RSS
These complex spacing issues only occur when mixing “high” and “low” VT cells. If your mixed VT design comprises of just “high” and “regular” or “regular” and “low” VT cells then these complex spacing issues can be avoided.
John,
Thanks for the feedback. That’s correct this requirement pops up only when mixing High/Low Vt.
Thanks,
Godwin
You can use tcl script to insert the right filler cell also
Hi,
I wonder why it is not a problem between regular and high or between regular and low. Can you explain? Thanks.
Ed,
One of the reason is how mask is created for Normal/Low/High Vt cells. The impact on normal cell is very minimal.
Thanks,
Godwin
Hello,
I attended recent seminar at Bangalore wherein it was mentioned we can have access to the low power methodology manual online book, but I am not able to. Also in this open community website, when I tried clicking on book club- LPMM book link, it leads somewhere.
I hope this manual would contain all such useful tips to consider in dealing with low power designs. But how to access it..
Hello,
You can download the LPMM book through Solvnet.
Thanks,
Godwin
Hi, Surendranath,
Please go to http://www.synopsys.com/lpmm or http://www.arm.com/lpmm for more information about the “Low Power Methodology Manual” (LPMM).
There’s a button to click on there to get the free .pdf electronic edition. All you need is a SolvNet ID.
For your information, more than 4,000 people have downloaded their own free copy so far.
-Phil
hello sir, nice to see the details regarding Multi-Vt, i came to know a lot theoritically about multi-Vt, but i have a doubt how is going to provide this multi-Vt libraries, how to identify that a given library has this Multi-Vt facilty or not, can u tell me is there any way that i can download or get access to these Multi-Vt libraries so that i can work in low power domain. if possible please mail to my i.d “mathew.bablu20@gmail.com” , thanks