Welcome to the Inside Protocol Verification BLOG! Inside Protocol Verification is intended to bring you the latest scoop in bus verification. Our gang of protocol verification experts will be sharing their thoughts on the thorny issues in today's protocols, the latest features in the Verification IP space and the best protocol verification methodologies.
Hi, my name is Bernie DeLay and I'm the R&D Director responsible for Verification IP here at Synopsys. I came to Synopsys via the acquisition of Qualis where we had developed our own version of VIP which we coined DVCs. I come from the trenches of ASIC design & verification and over the years have lead several GPS ASIC development projects, served as a verification consultant and even taught classes in languages like VHDL, Verilog and 'e' (yes that 'other' company's language). I will be sharing my thoughts on issues that affect the whole protocol verification space. Hope you enjoy and maybe learn a trick or two in the Inside Protocol Verification blog!
My name is Steve McMaster and I'll be covering OCP on the blog. I've been working in EDA for 20+ years, with a few years spent developing schematic capture and board design tools, but many more years spent working in the verification arena. I'm currently the engineering lead for the Synopsys VIP for OCP, and I'm also the chair of the OCP-IP Functional Verification Working Group. I was a core team member for both the AXI and OCP-IP VIP development efforts, and have also been involved in the ongoing development for most of the existing Synopsys VIP products. My main focus on these projects has been in the areas of functional coverage, assertions, SystemVerilog, and VMM. So although my focus is going to be OCP, I consider all of these areas fair game for the blog.
Hi, I'm Jay Hopkins, Manager for the DesignWare VIP CAE Team here at Synopsys. I have been involved in design and EDA for nearly 25 years now; everything from missile guidance to barcode scanners to hardware/software co-verification to "plain old" verification - quite the gamut. I dabble in a variety of protocols here: AMBA, PCIe, Ethernet, as well as high level work on overall usage. I look forward to sharing my knowledge and views on protocol verification in this blog.
Hi, my name is Charles Li, CAE in the DesignWare VIP group at Synopsys and I am currently supporting the USB VIP models. I've been in hardware design and verification longer than I care to admit (anybody recall the best lead to use on vellum?). I've worked on ASICs, PC boards, full systems, and even software, but along the way, I figured out that verification is what really interested me. I consulted for companies on verification methodology for several years before joining Synopsys and there are a few hundred engineers out there using the techniques that I taught. I'm looking forward to contributing my insights and opinions to the 'Inside VIP' blog.
Hi, my name is Meni Jayaswal, CAE in the DesignWare group at Synopsys and I am currently supporting both AMBA 2.0 and AMBA 3 AXI Implementation IP and Verification IP. I have both design and verification experience and have been working in EDA for 8+ years, mainly focusing on infrastructure IP for ASIC/SoC designs. This includes DesignWare Building Block IP, complex Datapath IP, Microcontrollers and Synthesizable and Verification IP for AMBA. I am looking forward to share my views and learn new things in the protocol verification space in this blog.