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Board index » Verification

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Forum		Topics	Posts	Last post
Mark forums read
	Meet Your Moderator(s) Bios of your moderators Moderator: Mike Bartley	1	1	Fri Dec 07, 2007 3:30 pm Synopsys_Ron
	Digital Verification Moderator: Mike Bartley	57	129	Wed Jan 20, 2010 1:29 am phoenixson
	AMS Verification This forum is used to discuss analog/mixed-signal simulation topics. Moderator: Synopsys_Bradley	6	13	Fri Jun 12, 2009 4:39 pm adielkhan_snps

Verification

Moderator: Mike Bartley

Page 1 of 1

[ 17 topics ]

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Author

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Last post

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Sun Feb 07, 2010 11:00 am

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telecoms

Fri Feb 05, 2010 10:59 am

telecoms

AHB verification problem

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Wed Feb 03, 2010 12:55 am

ukjklm

VCS make error

moliel

244

Tue Feb 02, 2010 2:46 am

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sellphone1

118

Fri Dec 18, 2009 5:57 am

sellphone1

VCS error: Error-[RILIP] Register in low conn of input port

rashmikant

199

Mon Nov 02, 2009 10:28 am

rashmikant

VCS systemverilog coverage, no simv.vdb generated

rajat.asic

303

Fri Oct 02, 2009 4:51 am

rajat.asic

heating of a component in Hspice simulation

anduca

2910

Tue Sep 23, 2008 2:16 am

anduca

query on warning msg during synthesis with dc

cosmonutt

3199

Wed Sep 03, 2008 10:43 am

cosmonutt

How can i plot gain in hspice

tauhid035

3249

Mon Sep 01, 2008 3:25 am

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reddy_bv

3335

Tue Jul 22, 2008 11:31 pm

reddy_bv

Advanced High-Level Verification Market Penetration

ipa4me

2997

Mon Mar 17, 2008 3:44 pm

ipa4me

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Board index » Verification

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