Hi Jonathan,

Yes! The top priorities expressed by users are to simulate faster, bigger… (and always cheaper – UGH!). You can add ease-of-use to that as well, which is somewhat more subjective but includes the language compatibility issues that you mentioned. Unfortunately, marketers have a bad habit of trying to create false and irrelevant differentiation by attacking how a competing tool gets there, rather than focusing on the end result and what users really need. Hence my reaction to those who would assert that hierarchy or some other technique that delivers real tangible benefit to the user is a bad thing. As I said in my earlier post… that is Red Herring propaganda, and is not the least bit beneficial to users.

I am especially interested in your last comment: "Don’t expect me to use a different verification language for extracted transistor level simulation than I use for the rest of my functional verification". You and I have talked about that for a bit in person, but if you have the time to expand on the topic here it would be very valuable. How would you like to see the functional verification capabilities of System Verilog VMM (for example) extended to include mixed-signal blocks down to the transistor level?

-Mike

Don’t expect me to use a different verification language for extracted transistor level simulation than I use for the rest of my functional verification.