NanoTime is our transistor-level static timing product for custom designs. Since Custom Designer is for custom design too it was natural that we’d integrate the two tools together. Released in June of 2010, the NanoTime integration into Custom Designer lets users do concurrent timing and SI analysis for designs of up to 6 million devices and see the whole timing picture in schematics and layout.

We are pretty excited about this new integration and held a webinar on the topic this week. If you missed, don’t worry, it is archived on our website and you can watch it here.

Fred

Getting to the end-game faster in a chip design project is one of the driving forces for EDA. As EDA tools have matured over the years parts of the design flow have emerged as a major block of time. In custom design, the layout phase of blocks has become one area that needed serious attention. This phase often occupies as much 60 percent of the overall time for a given block and is an obvious target for productivity enhancers in a custom design tool.

Rather than trying to completely automate away the layout phase (as some have tried) we chose a different path. In analog designs the layout designer must have complete manual control of the layout so how do you automate that?

We chose a new path… we decided not to enforce our automation on designers but rather give them a toolbox of powerful new features that simplify their jobs and help get it done quicker. This is the first in a series of blog entries that will feature some of the ideas our team came up with after talking to many, many layout engineers.

Today’s topic is zooming and it’s evil twin counting grids. Layout designers often spend a great deal of time zooming into a region to start a wire, then zooming out to route it followed by a zoom back in to finish aligning the end of the wire. That’s a lot of clicks and often the designer has to go back across the wire counting grids and moving segments to make sure that he hasn’t violated the rules.

What if you could wire at high-altitude and eliminate the zooms? What if you could click near a terminal or a gate and have the new wire adopt the width, snapped to and pre-aligned with the terminal and just start wiring immediately?

We call it “SmartConnect” and it does just that. Another cool feature is SmartConnect’s “Alignment Markers” that make it obvious when you are aligned with the left, center or middle of another object.

Sounds simple but these features enable very rapid wiring without forcing the layout engineer to accept somebody else’s idea of what makes a good layout.

‘Til next time, keep wiring away and stay tuned. We’ve got a lot more stuff in the pipe for our next release that I think you will really like…

Fred

I was recently at an offsite where CAD engineers, Designers, and Custom Designer developers were all present. We were reviewing capabilities and deployments of Custom Designer in our IP business. One of the CAD engineers was reviewing some capabilities they had implemented using Hercules manipulation of GDS that allowed analog designers to better “see” their designs and optimize the layout.

One of the Custom Designer developers  said, “That capability looks a lot like this new feature that will be released in the up coming version of Custom Designer.” We all got VERY excited when he then demonstrated the beta version of this new feature to the assembled group. It was really cool and very useful. We then asked for a minor extension of the feature and he had that up and running in a trial tcl script within the hour. Sweet. We can hardly wait for the next release.

Later that night at dinner, one of the corporate apps engineers came up to me and said, “You don’t remember do you? I visited you 7 months ago with a list of planned features for CD and you looked it over and said –  “these are all OK but what would be really nice is if you could…” and then you described this new feature. We thought it was a great idea and put it at the top of the list.” I then told him that it was no wonder I had liked the new feature so much but I also told him I was terribly disappointed. When he asked why I was upset I said “Well if I had remembered I had suggested it I could have said ‘7 months – what took you so long!’”.

So when you see the next version of Custom Designer, there is at least one really cool feature that will blow you away (I haven’t seen the other cool one yet – just heard about it). You will know which feature it is because it is so useful. You will also know how we feel to work with an analog design tool that is growing and improving DAILY with developers who listen to us – how sweet it is!

Bob Lefferts

Hi Everybody!

First my apologies for our silence over the past couple of weeks. We’ve had our head down in preparation for and the delivery of the 47th Design Automation Conference in Anaheim last week (47? Really?)

Synopsys had an outstanding DAC this year and had many announcements to go with it. In addition to our main booth, we showed Custom Designer, HSPICE and CustomSim at a number of different venues throughout the show and that kept us, ah, rather busy.

Our demo suites were jammed and we hosted numerous customers, editors, analysts, breakfasts, lunches and dinners and the transcripts of many of those will be available soon. Stay tuned.

The show is over and now that we can breath, we’ll get back on track with some new posts about some great new technology we have coming up.

Fred

Today’s Guest Blogger is Dwayne Holst, Corporate Applications Engineer for CustomExplorer and Custom WaveView at Synopsys.

Running analog regressions in a production chip design flow is hard enough without having to sort through the results by hand. While the majority of the thousands of simulations are probably good, the risk of missing a problem is the risk of a bad tape out (and then you have to fill out a lot of paperwork, there are more questions and it’s generally not a good thing).

Last year, we introduced a new feature in CustomExplorer to help out with this tedious manual process.

Called “Batch Waveform Compare”, this feature automates the comparison of simulations runs in batch and alerts the user to the problems.

Waveform Compare can be used early on in the design phase. Designers can compare waveforms from RTL, down through to the device level and make sure that your design is converging on the spec. The final use of Waveform Compare tests the results of extracted parasitic simulations to help quickly isolate problems.

And it’s fast… One of our early adopters of Batch Waveform Compare saw their week of manual time required to “eyeball” 100 analog waveforms drop to just 15 minutes of Waveform Compare run time.

The user has complete control over the comparison algorithms. Tolerances for the x-axis (be it time, frequency…) can be set independently from the y-axis (be it voltage, current…) and Waveform Compare does the rest.

Here is a partial example of a rules file for waveform compare:

; Global Parameters
v_tolerance 5mv
i_tolerance 1ma
a2d_threshold 2.5v

; Aliases
Alias stable_period “start=5ns, stop=16ns”

; Rules
Rule v_check begin
   Master gold2.dat
   Step 0.1ns
   v_tolerance 1mv
   v_reltol -0.01
end

rule mono_chk begin
   monotonicity_check
end

…

; Checks
Check begin
   target “t1.dat t2.dat”
   signal “*”
   time_range “0ns, 6ns”
   rule “initial_v_check”

   target “t1.dat t2.dat t3.dat”
   signal “s1, s2, s3”
   time_range stable_period
   rule “v_check”
end

The result of this rule file applied against the simulation results
$> sx –compare compare.rules
   *** loading waveform file gold2.dat … ***
   *** loading waveform file t1.dat    … ***
   *** loading waveform file t2.dat    … ***
[COMPARE] master file    : ‘gold2.dat’
[COMPARE] master file    : ‘t1.dat’

# comparing signal ‘v(in1’

x-axis			master	0|test/IN1
1.0500E-08	1.650000	[1]		[0]
1.1000E-08	3.300000	[1]		[0]
# end of difference list
…

Waveform compare is a powerful tool in CustomExplorer and can be used to significantly improve design regression productivity. Have fun with it.

Dwayne

About Dwayne

Dwayne strives to be a cool dad and he’s an EDA geek. He also pretends to be a Southerner although he’s really a California Yankee living in North Carolina.