Hi All,

The registration page for Synopsys’ DAC events went live last week, with several AMS-related topics that I invite you to check out. I previously told you all about the AMS Breakfast panel discussion on Tuesday morning, June 10, focusing on the topic “AMS Verification and Moore’s Law… solutions for 45nm and beyond“. Registration for the breakfast is now open as well.

On Monday (June 9) through Wednesday (June 11), you have the opportunity of attending presentations in Synopsys’ Demo suites on:

• Mixed-Signal Circuit Design and Verification with Discovery™-AMS and Synopsys’ Custom Environment (twice a day)
  
• Transistor-Level Design Analysis and Sign-Off Using Star-RCXT®, HSIM™ and HSPICE®

You can also start off your day on Wednesday morning with another stimulating discussion at the Interoperability Breakfast. The topic for this year’s program is Raiders of the Locked Art: Opening the Treasure with Interoperable PDKs, which addresses the issue of custom analog design interoperability through OpenAccess.

I am also going to be in the Synopsys booth for another “Meet the Bloggers” opportunity. Come on by and say hello!

-Mike

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AMS verification

Design Automation Conference

Open Access

Transistor-level verification Star-RCXT

Hello Everyone,

The Design Automation Conference will take place this year in Anaheim-CA, on June 8-13. (OK… insert your own Mickey Mouse jokes here ________ )

I hope to see many of you at DAC, but if you were not planning to attend perhaps I can attract you with the Synopsys AMS Verification Breakfast that will take place on Tuesday morning, June 10th. The theme for this year’s panel discussion is “AMS Verification and Moore’s Law… solutions for 45nm and beyond“. If you have attended the AMS breakfast panels in the past, you know that they have been very interesting and entertaining affairs. This year we will explore the topic of AMS verification challenges, and how to address the issues that occur when “analog meets digital“. You need to go to this AMS Breakfast link to register, and those in attendance will have a chance to win a free Apple iPod Touch.

Our panelists this year:

Thomas J. Sheffler, PhD.
Sr. Principal Engineer
Rambus, Inc.

Jess Chen
Senior Staff Engineer
Qualcomm CDMA Technologies

Jeff McNeal
R&D Engineer
Synopsys IP Solutions Group

Henry Chang
Vice President
Designer’s Guide Consulting, Inc.

Following presentations by our panel of experts, you will have the opportunity for Q&A as well. It will be a great opportunity to network with colleagues who are active in the growing field of AMS verification, so I invite you to sign up today!

-Mike
Design Automation Conference AMS Verification analog digital

Hello Everyone,

Many of you may be familiar with the slogan that was created by Bill Clinton’s presidential campaign manager in 1992 - “It’s the economy, stupid”! James Carville created that message to keep the Clinton campaign focused on what he felt was the real issue at the time, so that they wouldn’t get sidetracked. Since that slogan became so memorable it has been re-used and adapted many times, and I think it is very appropriate to keep a similar message in mind when you are doing SPICE or Fast-SPICE simulation of your IC design.

“It’s the silicon, ******!” NOT the simulation!

OK, now I certainly don’t want any of you to stop using simulation, but I need to make what I think is a very important point here. I see many people get sidetracked by focusing on (what they think is) simulation “accuracy” when they should be focusing on the real goal; how accurately is your simulator predicting the behavior of the silicon? There is a HUGE difference.

Every designer knows that you are going to see a distribution of performance when you fabricate the chip. Simulation is just a guide to how the circuit will respond under one specific set of parameters… that I can guarantee you will never be seen in silicon exactly as it was modeled in simulation. It’s just a model! It’s kind of like trying to match two snowflakes. You will never find an actual chip that matches a given simulation to anything like 0.1%, yet people talk about 0.1% or better “accuracy” in SPICE. That’s nonsense.

So, that simulation that you are trying to make more “accurate”… if you think that tightening down on the RELTOL is going to make a difference… think again. Every simulation is just an idealized point in space! You can model the space in multiple dimensions by running process corners, parameter sweeps, and Monte Carlo but it’s still just a model of the potential operating space. Hopefully most of your silicon is going to live in that same space. If not, then you’ve got a real problem! The critical issue is to demonstrate that the simulation space covers your objective specs in such a way that you will get acceptable yield. And you can be assured that if you use a simulator that is identical to what your foundry uses to develop device models from the silicon, well… that’s as good as you can get.

What got me started on this topic today was an article I read over at SCDsource, which just has it completely dead wrong on the subject of simulator accuracy, by focusing on the infamous SPICE parameter known as RELTOL! I’ll leave it to you if you care to follow the link to find out where this came from, since I’d rather not repeat erroneous information here!

I think it’s critically important that analog designers not get sidetracked by claims of “SPICE accuracy”. That is all too often just another red herring. So here’s some irony for you… RELTOL has nothing to do with accuracy! RELTOL in SPICE simulators is a convergence control parameter! If you relax RELTOL you will get more numerical noise, if you tighten it up you will (hopefully) get less. That’s it! Which is why a loose RELTOL setting will show up as reduced SNR in something like an ADC simulation. None of it is real, it’s all just a numerical artifact.

DEFINITION:

RELTOL = x

Relative error tolerance allowed. (Default =.001 or .1%.). If the ratio of successive values in iteration are within RELTOL of one, this value is considered to have converged.

This definition, which you can find by following the RELTOL link above, says it all. But if you want another take on it, here’s how Ken Kundert described RELTOL in his book “The Designer’s Guide to SPICE and Spectre” (reference: K. Kundert, Springer; 1st edition: May 31, 1995, highlighting added by yours truly). I think that Ken and others have recognized that confusion over this topic is very common, since you can also find this excerpt on the Designers-Guide website:

Reducing reltol decreases the error in the results computed by the simulator, however no level of accuracy is guaranteed. Nor is any particular level of accuracy implied from a given value for reltol. In particular, setting reltol to 0.1% in no way implies that the accuracy attained by the simulator is 0.1%.

RELTOL only controls the amount of change in the values of node voltages that a simulator allows as it iterates from one point to the next. It’s all relative, and in this case it’s only relative to the value of the previous iteration. As Ken said, RELTOL has nothing to do with accuracy.

The key message is this and it goes for almost any product you buy, especially in EDA: Don’t get sidetracked by specmanship and red herrings.

Because ultimately, it’s not the simulator… it’s the silicon! If you don’t understand what a simulator control parameter does, please ask an expert. Don’t just “turn the knobs” like RELTOL hoping for a better result.

-Mike

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SPICE simulation accuracy
analog
RELTOL
red herrings
EDA tools

Hello Everyone,

This blog just celebrated its 6-month anniversary on March-28th, so I thought it might be interesting to stop and take a look at a Top-10 list of the most-read articles so far.

Using “post views” as a measure of popularity (i.e. how often someone clicked on a given post’s URL), here is the ranking of most often-viewed articles since the inception of Analog Insights on Sept-28th, 2007:

1. More on analog synthesis and the non-cognescenti

2. Red Herrings: separating the truth from the hype in SPICE verification tools

In a 3-way tie:

3. … Because digital design is so easy!

4. A few random notes from ISSCC

5. How to subscribe to my blog

Followed by:

6. Design Verification. Analog… meet digital. Digital… meet analog.

7. AMS Verification at DVCon - Part II

8. Hierarchy and Isomorphism in Fast-SPICE simulators

9. AMS Verification at DVCon - part I

10. Reports of the Death of AMS SoCs are Greatly Exaggerated

Is there anything that we can glean from this? Here are my thoughts, but as always - let me know if you agree… disagree… all opinions are welcome.

The one thing that the top 2 articles have in common is that, in each of them, I attempted to debunk myths and dispel misinformation that is all too prevalent in hyped-up EDA marketing campaigns. I believe that you - my readers - will only come back here if you are getting information that is truthful and relevant to your work in analog design and verification. No hype here!

In analog synthesis and the non-cognescenti I addressed the misguided notion that analog design needs to become more like digital, by pointing out that the natures of analog and digital design are so fundamentally different that the tools required are different as well. It is unfortunate that there are so many industry voices still out there in the media and blogosphere that just don’t get that. As in the 2nd most article that I discuss below, this sort of thing distracts from the real issues we should be addressing. The cognoscenti… those of you who actually do analog design… you get it. Thanks for making that article #1!

In Red Herrings, the topic was FastSPICE simulation - where I addressed marketing campaigns that treat EDA tools like they belonged in a beer commercial… taste great/less-filling.. that sort of thing. That article has been up at the top of the most-viewed list from the day it posted, so that tells me that you all want the truth about how the tools we (EDA) provide can help you solve your problems, and not differentiation through labeling that is better left in the supermarket aisles.

How to subscribe to my blog quickly jumped up to the top 5. Thanks to my colleague Karen Bartleson who publishes The Standards Game, for linking to that article on her blog. I hope that you are checking out the other blogs on this site as well, and that the subscription techniques that I described are helping you to keep up to date.

It was good to meet many of you at the recent SNUG R&D night, and hear in person about the issues in AMS design and verification that are important to you. Here is one of the pics from SNUG (used with the kind permission of Ron Ploof - Synopsys’ New Media Evangelist, SNUG San Jose 2008). On the left is my colleague Godwin Maben, author of the Low Power blog.

Let me know any ideas you have that will make this more helpful to you.

-Mike
AMS Verification SNUG Analog design

Hi All,

In an earlier post I showed how to subscribe to my blog through My Yahoo! and Google blog readers. Some of you may prefer to be notified of new posts on my blog in the same way that you receive your daily email messages in Microsoft Outlook. If you are using Outlook 2007, the process for adding a blog to your “inbox” is very easy.

If you click on the Tools >> Account Settings function in Outlook 2007 you will see the following window:

You can see that there is an RSS tab. Select that, and then click on “New…”

In the box for “Enter the location”, you can type the following URL, or cut & paste it from the address that that you get when you click on the RSS icon that you see at the top left corner of this page:

http://synopsysoc.org/analoginsights/?feed=rss2

The URL above is the RSS feed for my blog. After you have pasted (or typed) it into the “New RSS Feed” box as above, click “Add” and you will see the “RSS Feed Options” box below:

You can accept the defaults and click on “OK”.

Now, when you look at your list of folders in Outlook-2007, you will see that Analog Insights has been added to the RSS Feeds folder. The folder will update automatically when I create a new post, and you can then read it as email.

There you have it… a convenient way to get automatically updated, to read… and  save the latest posts from my blog.

Let me know how it works for you. I should note that to leave a comment, which I hope that you all do from time-to-time, you will need to return here to this site.

-Mike

p.s. Meet me on Monday, March 31 at SNUG - Santa Clara.

RSS feeds Outlok 2007